Design And Reuse SoC News Alert

January 25, 2005

Michael,
Welcome to issue of January 25, 2005 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: TRUE CIRCUITS, INC.

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These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25um to 90nm.
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Programmable LVDS Transmitter from Silicon & Software Systems Ltd.

AES Coprocessor (High Speed and Low Footprint) from M-Systems Ltd.

IEEE 1394b AVLink with 5C DTCP content protection from Wipro Technologies

8 bit 1 MHz Low Power Housekeeping ADC from Cadence Design Systems

Phase Locked Loop (PLL) Frequency Multiplier Core from Cologne Chip AG

Wanted IPs :

Compactflash controller card/device side

MVB Fledbus for train Soft IP

An IP core based approach to the on-chip management of heterogeneous SoCs

One Approach to IP Cores: Ten Years and Going Strong

Addressing IP Reuse with Formal Verification and Assertion Based Verification

Software synthesis for embedded systems

IP/SOC PRODUCTS

Innovative Silicon launches new Z-RAM technology that doubles embedded DRAM density for SoCs

Virage Logic Launches 'Silicon Aware IP' to Maximize Yield, Time-to-Volume at 130nm and Below

Actel Announces Immediate Availability of 90 Intellectual Property Cores for New ProASIC3 and ProASIC3E FPGA Families

NewLogic's WLAN IP Supports IEEE 802.11j Standard

Faraday announces its proprietary low power dissipation platform solution - PowerSlash

MIPS Technologies and Virage Logic Announce Lowest Cost, Lowest Power, Highest Performance 333 MHz Embedded Processor

New radio architecture meets medical implant designers' needs for higher performance and longer life

Tahoe RF Semiconductor Offers New Fractional-N Synthesizer

Mercury Computer Systems, Inc. Announces Availability of its Serial RapidIO-Based Silicon IP Core

STRUCTURED ASIC

Altera Unveils HardCopy II: Industry's Most Compelling Structured ASIC Solution

DEALS

Saifun Grants New License to Infineon for Development of Flash Memory Products

Transmeta Licenses Advanced Power Management and Transistor Leakage Control Technologies to Sony

A license agreement has been signed between Gaisler Research and EADS Astrium GmbH for the use of the Gaisler Research Floating Point Unit

MIPS Technologies 24Kc Core to Power Advanced Digital Set-Top Boxes; Scientific-Atlanta Licenses MIPS32 24Kc Core

BUSINESS

MoSys Strengthens Presence in Taiwan Markets; Signs Sales Representative Agreement with Terasic Technologies, Inc.

MoSys Signs Sales Representative Agreement with Crescendo Technologies Ltd.; Partnership Strengthens Market Presence in China

Virage Logic Expands Distribution Model; 'First Mover' Status Among Emerging Foundries Underscores Market Leadership

Transmeta Corporation Outlines Strategic Restructuring Plan; Growth Strategy to Focus on Licensing Intellectual Property

Samsung and LG Select Silicon Image as Preferred HDMI Supplier for 2005 Consumer Electronics Models

FINANCIAL RESULTS

Verisity Announces Record Revenue of $17.8 Million for Fourth Quarter Fiscal 2004

Virage Logic Reports First-Quarter Fiscal 2005 Results; Posts 46% Year-Over-Year Revenue Growth

MIPS Technologies Reports Second Quarter Fiscal 2005 Financial Results; Record License Activity Drives 7th Consecutive Quarter of Growth

Rambus Reports Fourth Quarter Earnings

LEGAL

Rambus Receives Summary Judgment Rulings Finding Patent Infringement in Hynix Case

MOSAID Initiates Litigation Against Hynix for Patent Infringement

Rambus Responds to Recent Hynix Press Statements; Calls on Hynix to correct misleading press statements regarding infringement

Green Hills Software to Fight Wind River Lawsuit

Federal Court Recognizes Value of Qualcomm's Intellectual Property and Issues Injunction against Misappropriation of Qualcomm's Trade Secrets by Maxim Integrated Products

Mosaid Settles Samsung Patent Litigation

IBM plan to open software patents seeds IP debate

EMBEDDED SYSTEMS

Agere Systems Announces General Availability of a Dual-Mode UMTS/EDGE, W-EDGE Baseband Solution for Mass-Market Multimedia Mobile Phones

Tensilica's V6 Automation Tools Speed SOC Design by Several Orders of Magnitude

FOUNDRIES

IBM and Chartered Extend Technology Development Agreement to 45 Nanometer

SilTerra to Provide Virage Logic's IPrima(TM) Foundation Platform to Its 130nm Process Customers

ARM Completes Prototype Demonstration And Operational Testing Of ARM7TDMI Processor Based On ASPLA 90-nm

FPGA/CPLD

Actel's Third-Generation Flash-Based Devices Set the Bar at $1.50 as Industry's Lowest Cost FPGA Solution

Actel to Offer Complete Hardware Support for Industry's Lowest Cost FPGA Solutions with New Programmer and Starter Kit

Altera Demonstrates 90-nm Leadership as New Low-Cost Cyclone II FPGAs Begin Shipping Early

Xilinx Announces Results for Third Quarter of Fiscal 2005

Altera Demonstrates 90-nm Leadership by Shipping World's Highest-Density, Highest-Performance FPGA

Latest Data Shows Xilinx Virtex-4 FPGAs Consume Less Than 1/10th The Power Of Competing FPGAs

EDA

CoWare Integrates SPW into Cadence System-to-IC Flow

iRoC Technologies Introduces Soft Error Design Solution Platform; First Product, SoCFIT, Provides Designers with Soft Error Analysis Capability to Reduce Risk

TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite

Renesas Technology Develops Automated Device Sizing System for High-Speed Digital/Analog Converters for SoC Use

OTHER

StarCore SC2400 Processor Core Wins "Best DSP Licensable Core" Analysts' Choice Award From Microprocessor Reports

SPONSORED BY: TEMENTO SYSTEMS

Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

Click here to know more about Temento

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Feb. 1-2, 2005
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